The BERTScope Bit Error Rate Tester Series provides a new approach to signal integrity measurements of serial data systems. Perform bit error rate detection more quickly, accurately, and thoroughly by bridging eye diagram analysis with BER pattern generation. The BERTScope Bit Error Rate Tester Series enable you to easily isolate problematic bit and pattern sequences, then analyze further with advanced error analysis that deliver unprecedented statistical measurement depth.
Key Features:
Pattern Generation and Error Analysis, High-speed BER Measurements up to 28.6 Gb/s
Fast Input Rise Time / High Input Bandwidth Error Detector for Accurate Signal Integrity Analysis
Physical Layer Test Suite with Mask Testing, Jitter Peak, BER Contour, and Q-factor Analysis for Comprehensive Testing with Standard or User-defined Libraries of Jitter Tolerance Templates
Integrated Eye Diagram Analysis with BER Correlation
Optional Jitter Map Comprehensive Jitter Decomposition - with Long Pattern (i.e. PRBS-31) Jitter
Patented Error Location Analysis™ enables Rapid Understanding of your BER Performance Limitations and Assess Deterministic versus Random Errors, Perform Detailed Pattern-dependent Error Analysis, Perform Error Burst Analysis, or Error-free Interval Analysis
Integrated, calibrated stress generation to address the stressed receiver sensitivity and clock recovery jitter tolerance test requirements for a wide range of standards
Sinusoidal jitter to 100 MHz
Random jitter
Bounded, uncorrelated jitter
Sinusoidal interference
Spread spectrum clocking
PCIe 2.0 & 3.0 receiver testing
F/2 jitter generation for 8xFC and 10GBASE-KR testing
IEEE802.3ba & 32G fibre channel testing
Electrical stressed eye testing for
PCI express
10/40/100 Gb Ethernet
SFP+/SFI
OIF/CEI
Fibre channel (FC8, FC16, FC32)
SATA
USB 3.1
InfiniBand (SDR, QDR, FDR, EDR)
Tolerance compliance template testing with margin testing
Integrated eye diagram analysis with BER correlation