Configured models contain the following attributes:
Digital DesignBER Testing 2G-12GB/sOption | Description |
---|---|
Pattern and Pseudo Random Pattern Sequence (PRBS) on Auxillary Data Output License | |
Half-rate clocking and Duty Cycle Distortion | |
Bit Recovery Mode | |
Symbol Error Ratio and Frame Error Ratio (SER/FER) Analysis | |
Analysis of 128b/132b coded Patterns | |
Pattern Generator and Error Detector 150 Mb/s to 12.5 Gb/s . Includes built-in clock data recovery | |
Extended Pattern Generator Data Rate to 14.2 Gb/s | |
Jitter Injection: built-in and calibrated periodic jitter, sinusoidal jitter, random jitter, bounded uncorrelated jitter | |
Spread Spectrum Clocking (SSC) | |
Automated Jitter Tolerance Compliance Suite | |
Interference Channel: Intersymbol Interference and Sinusoidal Interference | |
Material Pattern Generator and Error Detector | |
Upgrade Jitter Transfer Measurement | |
Adapter 3.5 mm female to 2.4 mm male |
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Product ID: P-536575
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Product ID: P-605759
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Product ID: P-605713
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Product ID: P-617897
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Product ID: P-617895
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Product ID: P-617896
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Showing 1 - 6 of 7 results