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快速报价: Keysight Technologies 16720A-016
Keysight Technologies 16720A-016
Data Pod and Lead Set, 2.5 Volt; for Keysight Model 16720A
型号
16720A-016产品类别
Oscilloscopes & Logic Analyzers制造商
Keysight Technologies配置型号包含以下特性:
Oscilloscopes & Logic Analyzers配置
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产品总览
The Keysight 16720A digital pattern generator module for Keysight´s 16900 Series and 16700 Series logic analysis systems is ideal for the functional testing of your digital design. The pattern generator is used to simulate infrequently encountered test conditions in hardware design and software program testing. You can also use a pattern generator to stimulate your electronic designs with ideal or faulty digital patterns for performing functional verification, debugging and stress testing.
| Benefits | |
| Digital Stimulus | Maximum stimulus clock: 300 MHz / 180 MHz (half / full channel) Memory depth in vectors: 16 M / 8 M (half / full channel) Maximum vector width: 120 bits / 240 bits (half / full channel) Standard logic level support: TTL, CMOS, ECL, PECL, LVPECL, LVDS 3.3 V, 2.5 V, 1.8V |
| Pattern Sequencing | SynaptiCAD tools convert .VCD files into .PGB files directly Convenient pattern entry with multiple number bases and pattern fills INIT block, user-defined macros, and loops simplify vector entry and facilitate repetitive runs Wait for External Event enables stimulus only when an external event occurs |
| Configuration Considerations | 48-channels per module, connect up to 5 modules for 240 channels Pattern Generator clock and data pods are ordered separately Pattern Generator Pods Order at least one clock pod for each module used as a master, and at least one data pod for every 8 output channels Compatible with 16900 and 16700 Series modular logic analyzers |
| Specifications | |
| Model 16720A | |
| Features | Parameters |
| Maximum Clock (full/half channel) | 180/300 MHz |
| Number of Data Channels (full/half channel) | 48/24 Channels |
| Memory Depth (full/half channels) | 8/16 MVectors |
Maximum Vector Width (5 module system, full/half channel) | 240/120 Bits |
| Logic Levels Supported | 5 V TTL 3-state TTL 3-state TTL/CMOS 3-state 1.8 V 3-state 2.5 V 3-state 3.3 V ECL 5 V PECL 3.3 V LVPECL LVDS |
| Editable Vector Size (full/half channels) | 8/16 MVectors |
| Specifications | |
| Pattern Generator Module 300 M Vector/Sec | |
| Model 16720A Options | |
| Options | Description |
| 011 | TTL Clock Pod and Lead Set OPT |
| 013 | Data pod and lead set, 3-state TTL/CMOS |
| 014 | TTL Data Pod and Lead Set |
| 015 | Clock pod and lead set, 2.5 volt |
| 016 | Data pod and lead set, 2.5 volt |
| 017 | Clock pod and lead set, 3.3 volt |
| 018 | Data pod and lead set, 3-state 3.3 volt |
| 021 | ECL Clock Pod and Lead Set |
| 022 | ECL Terminated Data Pod and Lead Set |
| 023 | ECL Unterminated Data Pod Lead Set |
| 031 | Clock pod and lead set, 5 volt PECL |
| 032 | Data pod and lead set, 5 volt PECL |
| 033 | Clock pod and lead set, 3.3 volt LVPECL |
| 034 | Data pod and lead set, 3.3 volt LVPECL |
| 041 | Clock pod and lead set, 1.8 volt |
| 042 | Data pod and lead set, 1.8 volt |
| 051 | LVDS Clock Pod and Lead Set |
| 052 | LVDS Data Pod and Lead Set |
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