Keysight Technologies N4880A

The N4880A reference clock multiplier fills a critical requirement for R&D and test engineers who need to characterize and release the next generation of PCI Express main boards, MIPI M-PHY chipsets and SD card UHS-II host devices.

With its support for multiple reference-clock rates, the N4880A will help you accurately characterize and verify standards compliance under easy-to-reproduce test conditions.

In common reference-clock architectures, where the host cannot be driven by an external reference clock it’s necessary to lock the stressed-pattern generator to the same system reference clock used by the receiver under test.

This is because the receiver under test also derives its sampling clock from this reference clock.

Locking the stressed pattern generator to the same reference clock as the receiver under test ensures accurate and reproducible jitter-tolerance test results.

The N4880A provides a multiplying phase-locked loop (PLL) which enables users to lock the pattern generator of J-BERT N4903B or ParBERT 81250A to a system reference clock.

Spread Spectrum Clocking (SSC) and low frequency jitter are fed through the N4880A up to its PLL loop bandwidth of 2 or 5 MHz.

The N4880A tolerates huge amounts of SSC for UHS-II reference clocks and offers excellent input sensitivity to handle very low voltage levels.

Physical Dimensions

(W x H x D)

Bench top with bumper and connectors:

228 x 59 x 240 mm (9.0 x 2.3 x 9.74 in)

Reference clock multiplier

Included accessories:

One 50 Ω termination, 3.5 mm;

USB cable;

CD-ROM with software and user documentation;

Functional Test Report;

ROHS addendum